66 search results - page 5 / 14 » Automated Property Verification for Large Scale B Models |
122
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FMCAD
2007
Springer
15 years 5 months ago
2007
Springer
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
138
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
132
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ENTCS
2006
15 years 1 months ago
2006
Bounded Model Checking (BMC) searches for counterexamples to a property with a bounded length k. If no such counterexample is found, k is increased. This process terminates when ...
110
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CMSB
2006
Springer
15 years 4 months ago
2006
Springer
Genetic regulatory networks have been modeled as discrete transition systems by many approaches, benefiting from a large number of formal verification algorithms available for the ...
100
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DAC
1998
ACM
16 years 2 months ago
1998
ACM
We describe the verification of the IM: a large, complex (12,000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructi...