106 search results - page 2 / 22 » Automated Source-Level Error Localization in Hardware Design... |
ISQED
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract—Silicon debug poses a unique challenge to the engineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overc...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
TVLSI
2008
13 years 6 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
SIGGRAPH
1993
ACM
13 years 10 months ago
1993
ACM
We describe two instances in which precise mechanical calibration of virtual environments equipment has been replaced by automated algorithmic calibration through software that en...
ASPDAC
2005
ACM
13 years 8 months ago
2005
ACM
In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addit...