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    ASYNC
    2000
    IEEE
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    Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
    15 years 1 months ago
    Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
    Download  www.cadence.com
    Ivan Blunno, Luciano Lavagno
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    ENTCS
    2006
    176views more  ENTCS 2006»
    Automatic Formal Synthesis of Hardware from Higher Order Logic
    14 years 9 months ago
    Automatic Formal Synthesis of Hardware from Higher Order Logic
    Download  www.cl.cam.ac.uk
    A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
    Mike Gordon, Juliano Iyoda, Scott Owens, Konrad Sl...
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