322 search results - page 35 / 65 » Automated Synthesis of Optimized Circuits for Secure Computa... |
68
Voted
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
102
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GECCO
2008
Springer
14 years 10 months ago
2008
Springer
The choice of an appropriate hardware representation model is key to successful evolution of digital circuits. One of the most popular models is cartesian genetic programming, whi...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
71
Voted
DAC
2007
ACM
15 years 10 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...