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ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Opportunities and challenges for better than worst-case design
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
Todd M. Austin, Valeria Bertacco, David Blaauw, Tr...
DAC
2001
ACM
15 years 10 months ago
Coupling-Driven Bus Design for Low-Power Application-Specific Systems
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
Youngsoo Shin, Takayasu Sakurai
DAC
2000
ACM
15 years 10 months ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang
DAC
2005
ACM
15 years 10 months ago
Race-condition-aware clock skew scheduling
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
DAC
2003
ACM
15 years 10 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...