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ASYNC
1997
IEEE
103views Hardware» more  ASYNC 1997»
15 years 1 months ago
Efficient Timing Analysis Algorithms for Timed State Space Exploration
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
Wendy Belluomini, Chris J. Myers
DAC
2009
ACM
15 years 10 months ago
Timing-driven optimization using lookahead logic circuits
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
Mihir R. Choudhury, Kartik Mohanram
DAC
1999
ACM
15 years 1 months ago
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
DAC
2002
ACM
15 years 10 months ago
Uncertainty-aware circuit optimization
Xiaoliang Bai, Chandramouli Visweswariah, Philip N...