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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 3 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
15 years 1 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
DAC
2003
ACM
15 years 10 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
73
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DAC
2009
ACM
15 years 10 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler
CORR
2002
Springer
93views Education» more  CORR 2002»
14 years 9 months ago
Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
Denis V. Popel