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ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
15 years 9 months ago
Round-Robin Arbiter Design and Generation
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of b...
Vincent John Mooney III, George F. Riley, Eung S. ...
COMPSAC
2002
IEEE
15 years 9 months ago
Formalizing Incremental Design in Real-time Area: SCTL/MUS-T
Achievement of quality in software design, while never easy, is made more difficult by the inherent complexity of hard real-time (HRT) design. Furthermore, timing requirements in...
Ana Fernández Vilas, José J. Pazos A...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
15 years 8 months ago
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed t...
Alexandros Bartzas, Stylianos Mamagkakis, Georgios...
DAC
2006
ACM
16 years 5 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DAC
2005
ACM
15 years 6 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...