Sciweavers

557 search results - page 22 / 112
» Automatic Abstraction for Verification of Timed Circuits and...
Sort
View
FDL
2007
IEEE
15 years 1 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
EH
2000
IEEE
183views Hardware» more  EH 2000»
15 years 2 months ago
A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...
69
Voted
ENTCS
2006
109views more  ENTCS 2006»
14 years 9 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...
SDL
2001
125views Hardware» more  SDL 2001»
14 years 11 months ago
Verification of Quantitative Temporal Properties of SDL Specifications
Abstract. We describe an approach for the verification of quantitative temporal properties of SDL specifications, which adapts techniques developed for timed automata [2]. With res...
Iulian Ober, Alain Kerbrat
ICFEM
2009
Springer
14 years 7 months ago
Verifying Ptolemy II Discrete-Event Models Using Real-Time Maude
Abstract. This paper shows how Ptolemy II discrete-event (DE) models can be formally analyzed using Real-Time Maude. We formalize in Real-Time Maude the semantics of a subset of hi...
Kyungmin Bae, Peter Csaba Ölveczky, Thomas Hu...