Sciweavers

557 search results - page 23 / 112
» Automatic Abstraction for Verification of Timed Circuits and...
Sort
View
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
15 years 6 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
HYBRID
2009
Springer
15 years 1 months ago
Trajectory Based Verification Using Local Finite-Time Invariance
Abstract. In this paper we propose a trajectory based reachability analysis by using local finite-time invariance property. Trajectory based analysis are based on the execution tra...
A. Agung Julius, George J. Pappas
FORMATS
2009
Springer
15 years 1 months ago
Stochastic Games for Verification of Probabilistic Timed Automata
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
ATVA
2006
Springer
153views Hardware» more  ATVA 2006»
15 years 1 months ago
Learning-Based Symbolic Assume-Guarantee Reasoning with Automatic Decomposition
Abstract. Compositional reasoning aims to improve scalability of verification tools by reducing the original verification task into subproblems. The simplification is typically bas...
Wonhong Nam, Rajeev Alur
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
15 years 1 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...