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SIGSOFT
2007
ACM
15 years 10 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
MJ
2007
14 years 9 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
ASPDAC
2004
ACM
15 years 1 months ago
2004
ACM
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
COMPSAC
2008
IEEE
15 years 4 months ago
2008
IEEE
This work introduces probabilistic model checking as a viable tool-assisted approach for systematically quantifying DoS security threats. The proposed analysis is based on a proba...
ICPR
2004
IEEE
15 years 11 months ago
2004
IEEE
There is increasing interest in the development of reliable, rapid and non-intrusive security control systems. Among the many approaches, biometrics such as palmprints provide hig...