557 search results - page 55 / 112 » Automatic Abstraction for Verification of Timed Circuits and... |
DATE
2010
IEEE
14 years 10 months ago
2010
IEEE
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
108
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EUROMICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
116
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APN
2005
Springer
14 years 11 months ago
2005
Springer
Abstract. We establish mutual translations between the classes of 1safe timed-arc Petri nets (and its extension with testing arcs) and networks of timed automata (and its subclass ...
FPGA
2010
ACM
14 years 7 months ago
2010
ACM
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
FPL
2009
Springer
15 years 1 months ago
2009
Springer
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...