557 search results - page 5 / 112 » Automatic Abstraction for Verification of Timed Circuits and... |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract--Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesig...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
69
Voted
ASYNC
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
AMAST
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...
HYBRID
1995
Springer
15 years 1 months ago
1995
Springer