557 search results - page 7 / 112 » Automatic Abstraction for Verification of Timed Circuits and... |
CSREAESA
2004
14 years 11 months ago
2004
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
VLSID
2003
IEEE
15 years 10 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
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ECBS
2007
IEEE
15 years 1 months ago
2007
IEEE
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
TCS
2002
14 years 9 months ago
2002
We consider the timed automata model of [3], which allows the analysis of realtime systems expressed in terms of quantitative timing constraints. Traditional approaches to real-ti...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
ound in BMC by Combining Constant Propagation and Abstraction Roy Armoni, Limor Fix1 , Ranan Fraer1 , Tamir Heyman1,3 , Moshe Vardi2 , Yakir Vizel1 , Yael Zbar1 1 Logic and Validat...