Sciweavers

101 search results - page 4 / 21
» Automatic Clock Abstraction from Sequential Circuits
Sort
View
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
13 years 11 months ago
ILP-based optimization of sequential circuits for low power
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
Feng Gao, John P. Hayes
CSREAESA
2006
13 years 7 months ago
Java Flowpaths: Efficiently Generating Circuits for Embedded Systems from Java
The performance of software executed on a microprocessor is adversely affected by the basic fetchexecute cycle. A further performance penalty results from the load-execute-store p...
Darrin M. Hanna, Michael DuChene, Girma S. Tewolde...
VTS
1996
IEEE
126views Hardware» more  VTS 1996»
13 years 10 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
FMCAD
2008
Springer
13 years 8 months ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Preserving synchronizing sequences of sequential circuits after retiming
Abstract We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining c...
Maher N. Mneimneh, Karem A. Sakallah, John Moondan...