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» Automatic Data Layout for High Performance Fortran
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DSD
2010
IEEE
137views Hardware» more  DSD 2010»
14 years 9 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
INFORMATICALT
2007
136views more  INFORMATICALT 2007»
14 years 11 months ago
Generic Multimedia Database Architecture Based upon Semantic Libraries
Semantic-based storage and retrieval of multimedia data requires accurate annotation of the data. Annotation can be done either manually or automatically. The retrieval performance...
Omara Abdul Hamid, Muhammad Abdul Qadir, Nadeem If...
ICASSP
2008
IEEE
15 years 6 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
CCGRID
2005
IEEE
15 years 1 months ago
The Composite Endpoint Protocol (CEP): scalable endpoints for terabit flows
We introduce the Composite Endpoint Protocol (CEP) which efficiently composes a set of transmission elements to support high speed flows which exceed the capabilities of a single...
Eric Weigle, Andrew A. Chien
SIGOPS
2008
123views more  SIGOPS 2008»
14 years 11 months ago
Comparative evaluation of overlap strategies with study of I/O overlap in MPI-IO
Many scientific applications use parallel I/O to meet the low latency and high bandwidth I/O requirement. Among many available parallel I/O operations, collective I/O is one of th...
Christina M. Patrick, Seung Woo Son, Mahmut T. Kan...