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» Automatic Formal Model Generation and Analysis of SDL
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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
15 years 8 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
IJCAI
2007
15 years 1 months ago
A Factor Graph Model for Software Bug Finding
Automatic tools for finding software errors require knowledge of the rules a program must obey, or “specifications,” before they can identify bugs. We present a method that ...
Ted Kremenek, Andrew Y. Ng, Dawson R. Engler
ICST
2009
IEEE
14 years 9 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...
ASE
2005
103views more  ASE 2005»
14 years 11 months ago
Component Verification with Automatically Generated Assumptions
Abstract. Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. The typical approach to verifying propertie...
Dimitra Giannakopoulou, Corina S. Pasareanu, Howar...