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» Automatic Generation of Heuristics for Scheduling
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MSE
2003
IEEE
104views Hardware» more  MSE 2003»
15 years 2 months ago
Internet-based Tool for System-on-Chip Integration
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...
David Lim, Christopher E. Neely, Christopher K. Zu...
FPL
2009
Springer
172views Hardware» more  FPL 2009»
15 years 2 months ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
70
Voted
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Efficient BMC for Multi-Clock Systems with Clocked Specifications
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
Malay K. Ganai, Aarti Gupta
SIGMOD
2012
ACM
234views Database» more  SIGMOD 2012»
12 years 12 months ago
BloomUnit: declarative testing for distributed programs
We present BloomUnit, a testing framework for distributed programs written in the Bloom language. BloomUnit allows developers to write declarative test specifications that descri...
Peter Alvaro, Andrew Hutchinson, Neil Conway, Will...
233
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DAC
2012
ACM
12 years 12 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie