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» Automatic Generation of Language-based Tools
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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
16 years 6 days ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
SIGADA
1998
Springer
15 years 4 months ago
Testing Generic Ada Packages with APE
Despite substantial research on methods and tools for testing reusable modules, little help is available for the tester in the eld. Commercial tools for system testing are widely ...
Daniel Hoffman, Jayakrishnan Nair, Paul A. Stroope...
ICALT
2006
IEEE
15 years 5 months ago
Hybrid System for Generating Learning Object Metadata
– Generating LOM for learning material is a complex and tedious task to be manually completed. Therefore, the current trend is to automate this process. However, there are severa...
Olivier Motelet, Nelson A. Baloian
FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 3 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
QSIC
2005
IEEE
15 years 5 months ago
Test Case Generation by OCL Mutation and Constraint Solving
Fault-based testing is a technique where testers anticipate errors in a system under test in order to assess or generate test cases. The idea is to have enough test cases capable ...
Bernhard K. Aichernig, Percy Antonio Pari Salas