41 search results - page 4 / 9 » Automatic Generation of Synchronous Test Patterns for Asynch... |
103
Voted
ICCAD
1994
IEEE
15 years 2 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
90
Voted
DAC
1999
ACM
15 years 2 months ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
60
Voted
IFIP
1999
Springer
15 years 2 months ago
1999
Springer
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
119
Voted
ATS
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
77
Voted
ASYNC
2000
IEEE
15 years 2 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...