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84
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DDECS
2007
IEEE
127views Hardware» more  DDECS 2007»
15 years 6 months ago
Instance Generation for SAT-based ATPG
— Recently, there is a renewed interest in Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT). This results from the availability of very powerful SA...
Daniel Tille, Görschwin Fey, Rolf Drechsler
EVOW
2001
Springer
15 years 4 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
122
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ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
15 years 6 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
15 years 5 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
110
Voted
TCAD
1998
119views more  TCAD 1998»
14 years 12 months ago
A controller redesign technique to enhance testability of controller-data path circuits
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak