41 search results - page 6 / 9 » Automatic Generation of Synchronous Test Patterns for Asynch... |
84
Voted
DATE
2006
IEEE
15 years 6 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
90
Voted
VLSID
2007
IEEE
16 years 21 days ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
114
Voted
MJ
2007
14 years 12 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
111
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ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
136
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NOCS
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...