179 search results - page 1 / 36 » Automatic High Level Assertion Generation and Synthesis for ... |
FDL
2007
IEEE
14 years 4 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
HASE
2005
IEEE
14 years 3 months ago
2005
IEEE
Checking various temporal requirements is a key dependability concern in safety-critical systems. As modelchecking approaches do not scale well to systems of high complexity the r...
IESS
2007
Springer
14 years 4 months ago
2007
Springer
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
VLSID
2003
IEEE
14 years 10 months ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
SEUS
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...