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DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 10 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
SAMOS
2005
Springer
13 years 11 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 10 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
CODES
2006
IEEE
14 years 10 days ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
ASPDAC
2004
ACM
110views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Embedded software generation from system level design languages
Abstract— To meet the challenge of increasing design complexity, designers are turning to system level design languages to model systems at a higher level of abstraction. This pa...
Haobo Yu, Rainer Dömer, Daniel Gajski