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121
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ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
15 years 7 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
LISP
2008
165views more  LISP 2008»
15 years 3 months ago
Adapting functional programs to higher order logic
Higher-order logic proof systems combine functional programming with logic, providing functional programmers with a comfortable setting for the formalization of programs, specifica...
Scott Owens, Konrad Slind
114
Voted
ICPP
2007
IEEE
15 years 9 months ago
Automatic Trace-Based Parallelization of Java Programs
We propose and evaluate a novel approach for automatic parallelization. The approach uses traces as units of parallel work. We discuss the benefits and challenges of the use of t...
Borys J. Bradel, Tarek S. Abdelrahman
100
Voted
DAC
2003
ACM
16 years 4 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
152
Voted
CSMR
2005
IEEE
15 years 9 months ago
Database Wrappers Development: Towards Automatic Generation
Wrapping databases allows them to be reused in formerly unplanned contexts, such as web-based applications or federated systems. Indeed, a wrapper can provide external clients of ...
Philippe Thiran, Jean-Luc Hainaut, Geert-Jan Hoube...