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» Automatic Performance Debugging of SPMD Parallel Programs
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IPPS
2006
IEEE
15 years 3 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
HPCA
2011
IEEE
14 years 1 months ago
Bloom Filter Guided Transaction Scheduling
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
EUROPAR
2010
Springer
14 years 8 months ago
A Language-Based Tuning Mechanism for Task and Pipeline Parallelism
Abstract. Current multicore computers differ in many hardware aspects. Tuning parallel applications is indispensable to achieve best performance on a particular hardware platform....
Frank Otto, Christoph A. Schaefer, Matthias Dempe,...
CCGRID
2004
IEEE
15 years 1 months ago
A Java-based programming environment for hierarchical Grid: Jojo
Despite recent developments in higher-level middleware for the Grid supporting high level of ease-of-programming, hurdles for widespread adoption of Grids remain high, due to (1) ...
Hidemoto Nakada, Satoshi Matsuoka
CASES
2007
ACM
15 years 1 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir