Sciweavers

35 search results - page 2 / 7
» Automatic Technology Mapping for Generalized Fundamental-Mod...
Sort
View
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
13 years 10 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
CASES
2007
ACM
13 years 10 months ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...
WWW
2008
ACM
14 years 7 months ago
Exploiting semantic web technologies to model web form interactions
Form mapping is the key problem that needs to be solved in order to get access to the hidden web. Currently available solutions for fully automatic mapping are not ready for comme...
Bernhard Krüpl, Robert Baumgartner, Wolfgang ...
CIKM
2010
Springer
13 years 4 months ago
Automatic schema merging using mapping constraints among incomplete sources
Schema merging is the process of consolidating multiple schemas into a unified view. The task becomes particularly challenging when the schemas are highly heterogeneous and autono...
Xiang Li 0002, Christoph Quix, David Kensche, Sand...
DAC
2006
ACM
14 years 7 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong