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DDECS
2009
IEEE
128views Hardware» more  DDECS 2009»
15 years 4 months ago
A fast untestability proof for SAT-based ATPG
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
Daniel Tille, Rolf Drechsler
ASPDAC
2001
ACM
112views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Parameterized MAC unit implementation
Ethernet communication devices, such as adapter, hub, bridge and switch, all follow IEEE 802.3 standard protocol. We have designed and implemented an integrated 10/100 Mbps Etherne...
Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen
TCAD
2011
14 years 4 months ago
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhig...
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
15 years 6 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
ITC
1999
IEEE
118views Hardware» more  ITC 1999»
15 years 1 months ago
Logic BIST for large industrial designs: real issues and case studies
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
Graham Hetherington, Tony Fryars, Nagesh Tamarapal...