25 search results - page 2 / 5 » Automatic Verification of Combined Specifications: An Overvi... |
WSC
2007
14 years 11 months ago
2007
This article gives an overview of a framework for automatically generating large-scale simulation models from a domain specific problem definition data schema, here semiconductor ...
SEKE
2005
Springer
15 years 3 months ago
2005
Springer
The paper presents an approach to support run-time verification of software systems that combines two existing tools, Prospec and Java-MaC, into a single framework. Prospec can be...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
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ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
FM
2006
Springer
15 years 1 months ago
2006
Springer
This paper presents the formal verification of a compiler front-end that translates a subset of the C language into the Cminor intermediate language. The semantics of the source an...