302 search results - page 12 / 61 » Automatic Verification of Timed Circuits |
136
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GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
135
Voted
AHS
2006
IEEE
15 years 10 months ago
2006
IEEE
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
139
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
125
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FMCAD
2004
Springer
15 years 7 months ago
2004
Springer
The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this paper we advocate a methodology to handle this probl...
143
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ICIW
2007
IEEE
15 years 7 months ago
2007
IEEE
Abstract-- Maintaining large websites and verifying their semantic content is a difficult task. In this paper we propose a framework for syntactic validation, semantic verification...