302 search results - page 3 / 61 » Automatic Verification of Timed Circuits |
153
Voted
FPGA
2005
ACM
15 years 9 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
129
Voted
DAC
1999
ACM
16 years 4 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
101
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ASYNC
2002
IEEE
15 years 8 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
125
Voted
CHDL
1993
15 years 4 months ago
1993
126
Voted
ENTCS
2006
15 years 3 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...