302 search results - page 47 / 61 » Automatic Verification of Timed Circuits |
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
134
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FPGA
2003
ACM
15 years 5 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
103
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DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
102
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DAC
2007
ACM
15 years 3 months ago
2007
ACM
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
106
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C3S2E
2010
ACM
15 years 25 days ago
2010
ACM
Propositional satisfiability solving, or SAT, is an important reasoning task arising in numerous applications, such as circuit design, formal verification, planning, scheduling or...