302 search results - page 48 / 61 » Automatic Verification of Timed Circuits |
CODES
2010
IEEE
14 years 9 months ago
2010
IEEE
Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottlene...
105
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DAC
2000
ACM
16 years 20 days ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
105
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ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
CHES
2006
Springer
15 years 3 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
ISPD
2003
ACM
15 years 5 months ago
2003
ACM
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...