302 search results - page 49 / 61 » Automatic Verification of Timed Circuits |
187
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
129
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CEC
2007
IEEE
15 years 5 months ago
2007
IEEE
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
157
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
126
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RE
2001
Springer
15 years 8 months ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
201
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MOBILIGHT
2010
15 years 1 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...