302 search results - page 49 / 61 » Automatic Verification of Timed Circuits |
141
click to vote
DAC
2006
ACM
16 years 20 days ago
2006
ACM
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
CEC
2007
IEEE
15 years 1 months ago
2007
IEEE
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
116
click to vote
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
RE
2001
Springer
15 years 4 months ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
153
click to vote
MOBILIGHT
2010
14 years 9 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...