302 search results - page 51 / 61 » Automatic Verification of Timed Circuits |
FPL
2009
Springer
15 years 4 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
103
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ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
116
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INTEGRATION
2006
14 years 11 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
DAC
2001
ACM
16 years 20 days ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
109
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AGP
1999
IEEE
15 years 4 months ago
1999
IEEE
Disunification is the problem of deciding satisfiability of a system of equations and disequations with respect to a given equational theory. In this paper we study the disunifica...