96 search results - page 1 / 20 » Automatic generation of equivalent architecture model from f... |
86
Voted
DAC
2004
ACM
15 years 6 months ago
2004
ACM
122
Voted
DAC
1995
ACM
15 years 4 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
111
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DAC
2002
ACM
16 years 2 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
103
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TVLSI
2008
15 years 1 months ago
2008
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
122
Voted
ICCAD
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...