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ATS
2003
IEEE
98views Hardware» more  ATS 2003»
15 years 2 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
SAC
2008
ACM
14 years 9 months ago
Towards automatic feature vector optimization for multimedia applications
We systematically evaluate a recently proposed method for unsupervised discrimination power analysis for feature selection and optimization in multimedia applications. A series of...
Tobias Schreck, Dieter W. Fellner, Daniel A. Keim
HPCA
2008
IEEE
15 years 9 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...
DAC
2006
ACM
15 years 10 months ago
Behavior and communication co-optimization for systems with sequential communication media
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
15 years 2 months ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar