90 search results - page 13 / 18 » Automatic generation of synthetic sequential benchmark circu... |
ICCAD
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
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INTEGRATION
2006
14 years 9 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
EUROPAR
2007
Springer
15 years 1 months ago
2007
Springer
How can sequential applications benefit from the ubiquitous next generation of chip multiprocessors (CMP)? Part of the answer may be a dynamic execution environment that automatica...
ICS
2001
Tsinghua U.
15 years 1 months ago
2001
Tsinghua U.
This paper presents a novel technique to perform global optimization of communication and preprocessing calls in the presence of array accesses with arbitrary subscripts. Our sche...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...