90 search results - page 15 / 18 » Automatic generation of synthetic sequential benchmark circu... |
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
DSD
2010
IEEE
14 years 8 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
ICML
2006
IEEE
15 years 10 months ago
2006
IEEE
The power and popularity of kernel methods stem in part from their ability to handle diverse forms of structured inputs, including vectors, graphs and strings. Recently, several m...
ASPDAC
2009
ACM
15 years 3 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...