47 search results - page 3 / 10 » Automatic memory reductions for RTL model verification |
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
VLSID
2003
IEEE
15 years 10 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
MICRO
2008
IEEE
14 years 10 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
ENTCS
2008
14 years 10 months ago
2008
This paper presents our solutions to some problems we encountered in an ongoing attempt to verify the micro-hypervisor currently developed within the Robin project. The problems t...
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PPOPP
2009
ACM
15 years 10 months ago
2009
ACM
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...