47 search results - page 5 / 10 » Automatic memory reductions for RTL model verification |
DBPL
1997
Springer
15 years 2 months ago
1997
Springer
Abstract. In the context of the object-oriented data model, a compiletime approach is given that provides for a significant reduction of the amount of run-time transaction overhead...
DAC
2003
ACM
15 years 11 months ago
2003
ACM
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...
104
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DAC
2008
ACM
15 years 11 months ago
2008
ACM
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
CONCUR
2008
Springer
14 years 11 months ago
2008
Springer
Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the firs...
101
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FMCAD
2008
Springer
14 years 11 months ago
2008
Springer
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...