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» Automatic memory reductions for RTL model verification
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VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
15 years 10 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
CCS
2008
ACM
14 years 12 months ago
Reducing protocol analysis with XOR to the XOR-free case in the horn theory based approach
In the Horn theory based approach for cryptographic protocol analysis, cryptographic protocols and (Dolev-Yao) intruders are modeled by Horn theories and security analysis boils d...
Ralf Küsters, Tomasz Truderung
ASPDAC
2001
ACM
126views Hardware» more  ASPDAC 2001»
15 years 1 months ago
A new partitioning scheme for improvement of image computation
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
Christoph Meinel, Christian Stangier
FMOODS
2008
14 years 11 months ago
VeriCool: An Automatic Verifier for a Concurrent Object-Oriented Language
Reasoning about object-oriented programs is hard, due to , dynamic binding and the need for data abstraction and framing. Reasoning about concurrent object-oriented programs is eve...
Jan Smans, Bart Jacobs 0002, Frank Piessens
SIGSOFT
2003
ACM
15 years 10 months ago
A strategy for efficiently verifying requirements
This paper describes a compositional proof strategy for verifying properties of requirements specifications. The proof strategy, which may be applied using either a model checker ...
Ralph D. Jeffords, Constance L. Heitmeyer