47 search results - page 8 / 10 » Automatic memory reductions for RTL model verification |
DAGSTUHL
2006
14 years 11 months ago
2006
Verification and Simulation share many issues, one is that simulation models require validation and verification. In the context of simulation, verification is understood as the ta...
DSN
2006
IEEE
15 years 4 months ago
2006
IEEE
The Solaris 10 Operating System includes a number of new features for predictive self-healing. One such feature is the ability of the Fault Management software to diagnose memory ...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
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CAV
1998
Springer
15 years 2 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
ENTCS
2006
14 years 10 months ago
2006
In this paper, we address the issue of the formal verification of real-time systems in the context of a preemptive scheduling policy. We propose an algorithm which computes the st...