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ISVLSI
2005
IEEE
69views VLSI» more  ISVLSI 2005»
15 years 3 months ago
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, E...
PAMI
2012
13 years 3 days ago
CPMC: Automatic Object Segmentation Using Constrained Parametric Min-Cuts
—We present a novel framework to generate and rank plausible hypotheses for the spatial extent of objects in images using bottom-up computational processes and mid-level selectio...
João Carreira, Cristian Sminchisescu
NOCS
2010
IEEE
14 years 7 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...
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IPPS
2008
IEEE
15 years 4 months ago
An adaptive parallel pipeline pattern for grids
This paper introduces an adaptive parallel pipeline pattern which follows the GRASP (Grid-Adaptive Structured Parallelism) methodology. GRASP is a generic methodology to incorpora...
Horacio González-Vélez, Murray Cole
AIRS
2010
Springer
14 years 7 months ago
Top-Down and Bottom-Up: A Combined Approach to Slot Filling
The Slot Filling task requires a system to automatically distill information from a large document collection and return answers for a query entity with specified attributes (`slot...
Zheng Chen, Suzanne Tamang, Adam Lee, Xiang Li, Ma...