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» Automatic microarchitectural pipelining
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NOCS
2007
IEEE
15 years 4 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
15 years 1 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
RTS
2000
143views more  RTS 2000»
14 years 9 months ago
Fast and Precise WCET Prediction by Separated Cache and Path Analyses
Precise run-time prediction suffers from a complexity problem when doing an integrated analysis. This problem is characterised by the conflict between an optimal solution and the c...
Henrik Theiling, Christian Ferdinand, Reinhard Wil...
FPL
2009
Springer
85views Hardware» more  FPL 2009»
15 years 2 months ago
Generating high-performance custom floating-point pipelines
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
Florent de Dinechin, Cristian Klein, Bogdan Pasca
SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
14 years 8 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker