302 search results - page 20 / 61 » Automatic microarchitectural pipelining |
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Improved branch prediction accuracy is essential to sustaining instruction throughput with today’s deep pipelines. We introduce piecewise linear branch prediction, an idealized ...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
APCSAC
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
FPGA
2004
ACM
15 years 3 months ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...