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» Automatic microarchitectural pipelining
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ISPASS
2005
IEEE
15 years 3 months ago
Performance Characterization of Java Applications on SMT Processors
As Java is emerging as one of the major programming languages in software development, studying how Java applications behave on recent SMT processors is of great interest. This pa...
Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
MICRO
2002
IEEE
109views Hardware» more  MICRO 2002»
15 years 2 months ago
Using modern graphics architectures for general-purpose computing: a framework and analysis
Recently, graphics hardware architectures have begun to emphasize versatility, offering rich new ways to programmatically reconfigure the graphics pipeline. In this paper, we exp...
Chris J. Thompson, Sahngyun Hahn, Mark Oskin
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 2 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
FPL
2007
Springer
150views Hardware» more  FPL 2007»
15 years 1 months ago
Discrete Event Simulation of Molecular Dynamics with Configurable Logic
: Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized ...
Josh Model, Martin C. Herbordt
CGO
2004
IEEE
15 years 1 months ago
Using Dynamic Binary Translation to Fuse Dependent Instructions
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
Shiliang Hu, James E. Smith