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» Automatic microarchitectural pipelining
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MAM
2008
114views more  MAM 2008»
14 years 9 months ago
Asymmetrically banked value-aware register files for low-energy and high-performance
Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Z...
ICIP
2001
IEEE
15 years 11 months ago
Towards automatic modeling of 3D cultural heritage
Exporting to cultural heritage methods and tools used in industrial areas, where the profits can justify high modeling costs, may only be a starting point for cultural heritage mo...
Marco Andreetto, Riccardo Bernardini, Guido Maria ...
ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
14 years 11 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
PPOPP
2010
ACM
15 years 4 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
14 years 7 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou