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» Automatic microarchitectural pipelining
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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 1 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
CVPR
2009
IEEE
16 years 4 months ago
Automatic Reconstruction of Cities from Remote Sensor Data
In this paper, we address the complex problem of rapid modeling of large-scale areas and present a novel approach for the automatic reconstruction of cities from remote sensor da...
Charalambos Poullis (CGIT/IMSC/USC), Suya You (Uni...
IESS
2007
Springer
156views Hardware» more  IESS 2007»
15 years 3 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
3DPVT
2004
IEEE
106views Visualization» more  3DPVT 2004»
15 years 1 months ago
Metrological Analysis of a Procedure for the Automatic 3D Modeling of Dental Plaster Casts
As well known, in the reconstruction of the 3D models through optical systems, the errors are due to the singleview acquisition error and to the 3D modeling procedure. The latter ...
Nicola Brusco, Simone Carmignato, Marco Andreetto,...
CODES
2010
IEEE
14 years 7 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem