302 search results - page 49 / 61 » Automatic microarchitectural pipelining |
104
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RSP
2008
IEEE
15 years 4 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
DICS
2006
15 years 1 months ago
2006
Dynamic Parallel Schedules (DPS) is a flow graph based framework for developing parallel applications on clusters of workstations. The DPS flow graph execution model enables automa...
CGF
2008
14 years 9 months ago
2008
In this paper, we propose a novel approach for automatic generation of visualizations from domain-specific data available on the web. We describe a general system pipeline that co...
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
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MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...